1. Field of the Invention
The present invention relates to a method for designing integrated circuits. More particularly, the present invention relates to a method for designing integrated circuits using a hierarchical design technique.
2. Description of the Related Art
A hierarchical design technique is widely used for designing integrated circuits. The hierarchical design effectively improves efficiency of the design of the integrate circuits.
A hierarchical layout method is disclosed in Japanese Patent No. 2980316. As shown in FIG. 1A, the hierarchical design method begins with floor planning of a top-level hierarchical cell (top-level layer). As a result, macros 101a, 101b and 101c and an interconnecting path 102 are incorporated in the top-level hierarchical cell. The interconnecting path 102 is used for transmitting a signal from the macro 101a to the macro 101c. The interconnecting path 102 is designed so as to pass through the macro 101a. 
The interconnecting path 102 is composed of interconnections 103, 104 and a repeater buffer 105. The repeater buffer 105 reduces a delay taken for a signal to be transmitted from the macro 101a to the macro 101c. 
As shown in FIG. 1B, the macro level design data (or low-level design data) representative of a layout of macros (or low-level hierarchical cells) is then generated from a top-level design data representative of the layout of the top-level hierarchical cell. In the example shown in FIG. 1B, the macro level design data representative of the layout of the macro 101b is generated from the top-level design data.
The process of the generation of the macro level design data is described below. At first, virtual terminals 106b, 106c are generated at intersections of the interconnections 103, 104 and the boundary of the macro 101b, respectively. The interconnection 103 is divided into an interconnection 103a and an interconnection 103b by the virtual terminal 106b. Similarly, the interconnection 104 is divided into an interconnection 104a and an interconnection 104b by the virtual terminal 106c. The information representative of the arrangements of the interconnection 103a and the interconnection 104a, which are located outside the macro 101b, is left in the top-level design data. On the other hand, the information representative of the arrangements of the interconnection 103b, the interconnection 104b, and the repeater buffer 105, which are located inside the macro 101b, is separated from the top-level design data and embedded into the macro level design data.
Next, the layouts of the interconnections 103b, 104b are modified to optically determined the layout inside the macro 101b on the basis of the macro level design data. The positions of the virtual terminals 106b, 106c and the repeater buffer 105 are not changed by the modification of the layouts.
In the conventional hierarchical design method, the interconnecting path is determined so as to pass through the macro 101b, and the interconnecting path is further embedded in the macro 101b when the macro is designed. This prevents the interconnecting path of the top-level hierarchical cell from taking a long way around the macro 101b, and thus reduces the delay of the interconnecting path of the top-level hierarchical cell.
However, the conventional hierarchical design method requires a merge of the top-level design data and the macro level design data before a timing analysis, because the typical timing analysis tool does not comply with the timing analysis of the LSIs by the conventional hierarchical design method. The necessity of the merge of the top-level design data and the macro level design data reduces the merit of concurrent layout designs of a plurality of hierarchical levels.
With reference to FIG. 2, a typical timing analysis tool requests the provisions of data representative of:
the waveform rounding parameter of an input signal to an input terminal 202;
the resistance of an interconnection connected to an output terminal 203 from which an output signal is outputted; and
the load capacitance of the output terminal 203. Here, the waveform rounding parameter implies the time taken for the input signal to rise up from a Low-level to a High level, or to trail from the High level to the Low-level. Typically, the time required for the input signal to rise from 10% of the High level to 90%, or to trail from 90% of the High level to 10% is used for representing the waveform rounding parameter. A delay of the macro is calculated during the timing analysis on the basis of the waveform rounding parameter of the input signal, the resistance of the interconnection connected to the output terminal, and the load capacitance of the output terminal.
The process of calculating a delay of a buffer included in the macro by a typical timing analysis tool is as follows. With reference to FIG. 3, let us suppose that the macro 201 includes a buffer 204 and an interconnection 205 connected to an output terminal of the buffer 204. The typical timing analysis tool calculates a delay Tg of the buffer 204 by the equation (1):
Tg=f1(Trf, R, C+Cin),xe2x80x83xe2x80x83(1)
where f1 is a predetermined function, Trf is the waveform rounding parameter at the input terminal of the buffer 204, R is the resistance of the interconnection 205 connected to the output terminal of the buffer 204, C is the capacitance of the interconnection 205, and Cin is the capacitance of an input terminal of another cell 206 to which the interconnection 205 is connected.
In addition, the typical timing analysis tool calculates a delay Tw of the interconnection 205 by the equation (2):
Tw=f2(R, C+Cin)+Trfxe2x80x2,xe2x80x83xe2x80x83(2)
where Trfxe2x80x2 is the waveform rounding parameter at the input terminal of the cell 206. The waveform rounding parameter Trfxe2x80x2 is calculated by the equation (3):
Trfxe2x80x2=f3(D, R, C+Cin),xe2x80x83xe2x80x83(3)
where D is a driving ability of the buffer 204 for outputting a signal to the interconnection 205.
With reference to FIG. 4, let us consider the case when the timing analysis is performed with respect to the macro 101b embedded in a LSI designed by the conventional hierarchical design method.
A delay T taken for a signal to be transmitted from a virtual terminal 106b to a virtual terminal 106c is given by:
T=Tw1+Tg1+Tw2,
where Tw1 is a delay of the interconnection 103b, Tg1 is a delay of the repeater buffer 105, and Tw2 is a delay of the interconnection 104b. 
From the equation (2), the delay Tw1 is given by:
Tw1=f2(R2, C2+Cin1)+Trf1,
where R2 is the interconnection resistance of the interconnection 103b, C2 is the interconnection capacitance of the interconnection 103b, Cin1 is the capacitance of the input terminal of the repeater buffer 105, and Trf1 is the waveform rounding parameter at the input terminal of the repeater buffer 105.
The waveform rounding parameter Trf1 can not be calculated by using the typical timing analysis tool, because the typical timing analysis tool does not have the function of receiving all parameters required to calculate the waveform rounding parameter Trf1. The waveform rounding parameter Trf1 is given by the equation (3) as follows:
Trf1=f3(D1, R1+R2, C1+C2+Cin1),
where D1 is the driving ability of a buffer 101a for outputting an input signal to the virtual terminal 106b, R1 is the resistance of the interconnection 103a connected to the virtual terminal 106b, C1 is the capacitance of the interconnection 103a. The typical timing analysis tool has the function of receiving the waveform rounding parameter of the input terminal to the virtual terminal 106b. However, the typical timing analysis tool does not have the function of receiving the driving ability D1, the interconnection resistance R1 and the interconnection capacitance C1, which are required to calculate the waveform rounding parameter Trf1.
Since the waveform rounding parameter Trf1 can not be calculated, it is impossible to calculate the interconnection delay Tw1 occurring on the interconnection 103b. 
Moreover, the typical timing analysis tool can not calculate the delay Tg1 occurring in the repeater buffer 105. From the equation (1), the delay Tg1 is given by:
Tg1=f1(Trf1, R2+R4, C3+C4+Cin2).
This formula proves that the calculation of the delay Tg1 requires the waveform rounding parameter Trf1 at the input terminal of the repeater buffer 105. As mentioned above, the waveform rounding parameter Trf1 can not be calculated by the typical timing analysis tool. Thus, the typical timing analysis tool can not calculate the delay Tg1.
As mentioned above, the typical timing analysis tool can not carry out the timing analysis of the macro 101b without merging the top-level design data and the macro level design data.
It is desired to provide a method and system for improving efficiency of designing an integrated circuit by separately performing timing analysis on and the top-level hierarchical cell and the low-level hierarchical cell (the macro) while providing the interconnecting path to pass through the low-level hierarchical cell.
Therefore, an object of the present invention is to provide a method and system for improving efficiency of designing an integrated circuit by separately performing timing analysis on the low-level hierarchical cell (the macro) and the top-level hierarchical cell while providing the interconnecting path to pass through the low-level hierarchical cell.
In order to achieve an aspect of the present invention, a method of designing a layout of an integrated circuit includes:
(A) incorporating a macro in a top-level hierarchical cell; and
(B) determining a layout of an interconnecting path provided in the top-level hierarchical cell, the interconnecting path transmitting a signal from a first position located outside the macro to a second position located outside the macro such that the interconnecting path passes through the macro. The interconnecting path includes:
first and second buffers placed substantially on a boundary of the macro, an output of the first buffer being electrically connected to an input of the second buffer,
a first interconnection connecting the first position to an input of the first buffer, and
a second interconnection connecting an output of the second buffer to the second position.
Preferably, the method further includes:
(C) determining a first maximum allowed delay of the first interconnection;
(D) determining a second maximum allowed delay for transmitting the signal from the input of the first buffer to the output of the second buffer;
(E) determining a third maximum allowed delay of the second interconnection,
the determining the layout of the interconnecting path including:
(F) determining a layout of the first interconnection such that a delay of the first interconnection is equal to or smaller than the first maximum allowed delay,
(G) determining a layout inside the macro such that a delay needed for transmitting the signal from the input of the first buffer to the output of the second buffer is equal to or smaller than the second maximum allowed delay, and
(H) determining a layout of the second interconnection such that a delay of the second interconnection is equal to or smaller than the third maximum allowed delay.
It is also preferable that the interconnecting path further includes a third interconnection connecting the output of the first buffer to the input of the second buffer, and that the determining the layout inside the macro is composed of:
(I) determining a layout of the third interconnection such that the delay needed for transmitting the signal from the input of the first buffer to the output of the second buffer is equal to or smaller than the second maximum allowed delay.
The determining the first, second and third maximum allowed delays is preferably composed of:
(J) determining a layout of a tentative interconnecting path connecting the first position to the second position, the tentative interconnecting path including:
first and second tentative buffers placed inside the macro and substantially on the boundary of the macro,
a first tentative interconnection connecting the first position to an input of the first tentative buffer,
a second tentative interconnection connecting an output of the first tentative buffer to an input of the second tentative buffer,
a third tentative interconnection connecting an output of the second tentative buffer to the second position,
(K) calculating a tentative total delay of the tentative interconnecting path,
(L) calculating a tentative inside delay needed for transmitting a signal from the input of the first tentative buffer to the output of the second tentative buffer, and
(M) determining the second maximum allowed delay on the basis of the tentative total delay and the tentative inside delay.
The second maximum allowed delay is preferably determined by:
TC2=TCxc2x7(T2/T0),
where TC2 is the second maximum allowed delay, TC is a total maximum allowed delay of the interconnecting path, T2 is the tentative inside delay, and T0 is the tentative total delay.
The determining the layout inside the macro preferably includes:
(L) determining an arrangement of the first and second buffers such that the arrangement is identical to a tentative arrangement of the first and second tentative buffers, and
(M) embedding the first and second buffers into the macro.
The determining the first, second and third maximum allowed delays is preferably further composed of:
(N) calculating a first tentative delay of the first tentative interconnection,
(O) determining the first maximum allowed delay on the basis of the tentative total delay and the first tentative delay.
The first maximum allowed delay is preferably determined by:
TC1=TCxc2x7(T1/T0),
where TC1 is the first maximum allowed delay, TC is a total maximum allowed delay of the interconnecting path, T1 is the first tentative delay, and T0 is the tentative total delay.
The determining the first, second and third maximum allowed delays is preferably further composed of:
(P) calculating a second tentative delay of the third tentative interconnection,
(Q) determining the third maximum allowed delay on the basis of the tentative total delay and the second tentative delay.
The third maximum allowed delay is preferably determined by:
TC3=TCxc2x7(T3/T0),
where TC3 is the third maximum allowed delay, TC is a total maximum allowed delay of the interconnecting path, T3 is the third tentative delay, and T0 is the tentative total delay.
In order to achieve another aspect of the present invention, a computer program is used for executing a method for designing a layout of an integrated circuit by a computer, the method comprising:
(A) incorporating a macro in a top-level hierarchical cell; and
(B) determining a layout of an interconnecting path provided in the top-level hierarchical cell, the interconnecting path transmitting a signal from a first position located outside the macro to a second position located outside the macro such that the interconnecting path passes through the macro. The interconnecting path includes:
first and second buffers placed substantially on a boundary of the macro, an output of the first buffer being electrically connected to an input of the second buffer,
a first interconnection connecting the first position to an input of the first buffer, and
a second interconnection connecting an output of the second buffer to the second position.
In order to achieve still another aspect of the present invention, a computer assisted design system used for designing a layout of an integrated circuit is composed of an input unit receiving a net list And a processor responsive to the net list. The processor is programmed to incorporating a macro in a top-level hierarchical cell on the basis of the net list, and to determine a layout of an interconnecting path provided in the top-level hierarchical cell on the basis of the net list. The interconnecting path transmits a signal from a first position located outside the macro to a second position located outside the macro such that the interconnecting path passes through the macro. The interconnecting path includes first and second buffers placed substantially on a boundary of the macro, an output of the first buffer being electrically connected to an input of the second buffer, a first interconnection connecting the first position to an input of the first buffer, and a second interconnection connecting an output of the second buffer to the second position.